meeting date: 29 nov 2005
attending: Arpad Muranyi, Todd Westerhoff, Bob Ross, Ian Dodd, Mike LaBonte
           Shang Li, Walter Katz, Ken Willis, Paul Fernando
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Review of ARs:

Arpad to change IBIS buffer implementation to have two input control thresholds
- not yet, waiting to finish the VHDL-A(MS) library before making any
  more changes on the Verilog-A(MS) library so that they can be synched up
  completely.

Mike finish documentation examples.
- not yet

Ian and Arpad write BIRD
- draft sent out, would like feedback

Arpad contact Paul Fernando to join our calls
- done

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AR: all review draft BIRD proposal

Paul Fernando
- Areas where we need help
  - Script to extract IBIS data to produce Verilog-A instance
  - Same for VHDLA
- Could use some existing parser?
  - Paul can check into this
  - s2ibis3 is Java
  - IBIS parser is in C, and licensed
    - has become difficult to manage
    - is the official reference
    - NCSU does not have the license
  - Mike has a PERL parser that Paul can look at
    - has 2 layers
  - Atul wrote something ???
- Paul needs to look at our files
- Also could use help converting more templates
  - 4 or 5 have been done
  - could build 4 tap and 6 tap, etc.
  - LVDS ?
  - DDR ?
    - AMS good for multi-stage drivers
- Need testing most of all

AR: Mike send PERL parser to Paul
AR: Paul choose a parser platform

What does macro approach do that IBIS doesn't?
- IBIS structure is already defined
  - even [Driver Schedule] is pre-defined
- macro approach is for structures not yet thougt of

Real question: why create Verilog and VHDLA implementations of B element?
  - easy to translate tables
  - hard part is k/t function
- Is AMS implementation of B element accurate?
  - difficult to get C_comp right
  - existing tools have secret sauce to make it work

AR: Arpad to change IBIS buffer implementation to have two input control thresholds
AR: Mike finish documentation examples.

Discussion of Shang Li's questions
- No conclusions reached

AR: Ken will send out something to the reflector about the syntax changes that the Verilog-AMS LRM2.3 may introduce to the array declaration.

Scheduled meetings
- No meeting Dec 27 and maybe not Dec 20 either.

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Next meeting: Tuesday 06 dec 2005